I. Field of the Disclosure
The technology of the disclosure relates generally to metal-oxide semiconductor (MOS) standard cells, and particularly to vertical scaling in MOS standard cells which affects source-drain tip-to-tip spacing between MOS standard cells.
II. Background
Transistors are essential components in modern electronic devices. Large numbers of transistors are employed in integrated circuits (ICs) in many modern electronic devices. For example, components such as central processing units (CPUs) and memory systems each employ a large quantity of transistors to form logic circuits and memory devices. More specifically, each IC in a component employs multiple transistors interconnected in a particular pattern to achieve the desired function of the electronic devices employed in the IC.
In this regard, processor-based computer systems can include a vast array of ICs, each of which is designed to perform one or more particular functions. Each IC has a complex layout design comprised of multiple IC devices formed from a large number of transistors. Metal-oxide semiconductor (MOS) standard cell circuits are often employed to assist in making the design of ICs less complex and more manageable. In particular, MOS standard cell circuits provide a designer with pre-designed cells corresponding to commonly used IC devices that conform to specific design rules of a chosen technology. As non-limiting examples, complementary MOS (CMOS) standard cell circuits (i.e., standard cell circuits that include both a P-type dopant and an N-type dopant semiconductor material diffusion region to form both P-type MOS (PMOS) and N-type MOS (NMOS) transistors) may include logic gates, inverters, multiplexers, and adders. Using CMOS standard cell circuits enables a designer to create ICs having consistent layout designs, thereby creating a more uniform and less complex layout design across multiple ICs, as compared to custom-designing each circuit.
Conventional MOS standard cell circuits are formed using one or more MOS standard cells fabricated using process technologies that form device elements with a pre-defined technology node size. For example, a process technology may be employed to fabricate a conventional MOS standard cell with device elements approximately fourteen (14) nanometers or ten (10) nm wide. Process improvements continue to enable decreased technology node size, which allows a higher number of device elements, such as transistors, to be disposed in less area within a circuit. As technology node size scales down, metal lines within a conventional MOS standard cell also scale down to reduce overall area consumption. For example, as the technology node size is reduced, supply rails that conventionally have a rail width approximately equal to three (3) times a line width of metal lines in a MOS standard cell may be vertically scaled to have a rail width approximately equal to the line width. Such vertical scaling of the rail width reduces the overall height of a MOS standard cell, and thus, the overall area of the MOS standard cell circuit. However, vertically scaling a MOS standard cell to reduce the overall height results in less space in which transistor elements such as source and drain regions may be formed. The reduced space makes it more difficult to maintain spacing between such elements that satisfies design rules of a corresponding fabrication process, wherein violation of such design rules causes erroneous operation of a MOS standard cell circuit.